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| ILX554B 2048-pixel CCD Linear Sensor (B/W) for Single 5V Power Supply Bar-code Reader Description The ILX554B is a rectangular reduction type CCD linear image sensor designed for bar code POS hand scanner and optical measuring equipment use. A built-in timing generator and clock-drivers ensure single 5V power supply for easy use. Features * Number of effective pixels: * Pixel size: * * * * * 22 pin DIP (Cer-DIP) 2048 pixels 14m x 56m (14m pitch) Block Diagram Readout gate pulse generator CCD analog shift register Readout gate Clock-drivers * Operating temperature * Storage temperature Pin Configuration (Top View) VOUT NC NC SHSW CLK NC NC NC NC NC ROG 1 1 2 3 4 5 6 7 8 9 10 2048 11 6 -10 to +60 -30 to +80 V C C Clock pulse generator/ Sample-and-hold pulse generator 22 21 20 19 18 17 16 15 14 13 12 NC NC VDD GND NC NC NC NC NC NC * Output amplifier * S/H circuit Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E01752A22-PS VOUT NC 1 GND 19 VDD 20 CLK 5 SHSW Absolute Maximum Ratings * Supply voltage VDD Mode selector S2046 S2047 S2048 D33 4 D37 D38 D32 S1 S2 S3 D13 D14 Single 5V power supply Ultra-high sensitivity Built-in timing generator and clock-drivers Built-in sample-and-hold circuit Maximum clock frequency: 2MHz ROG 11 ILX554B Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 Symbol VOUT NC NC SHSW CLK NC NC NC NC NC ROG Description Signal output NC NC Switch (with S/H or without S/H) Clock pulse input NC NC NC NC NC Readout gate pulse input Pin No. 12 13 14 15 16 17 18 19 20 21 22 Symbol NC NC NC NC NC NC NC GND VDD NC NC NC NC NC NC NC NC NC GND 5V power supply NC NC Description Mode Description Mode in use With S/H Without S/H Pin 4 (SHSW) GND VDD Recommended Supply voltage Item VDD Min. 4.5 Typ. 5.0 Max. 5.5 Unit V Input Clock voltage Condition1 Item VIH VIL Min. 4.5 0 Typ. 5.0 -- Max. VDD 0.5 Unit V V 1 This is applied to the all pulses applied externally. (CLK, ROG) Clock Characteristics Item Input capacity of CLK Input capacity of ROG Symbol CCLK CROG Min. -- -- Typ. 10 10 Max. -- -- Unit pF pF -2- ILX554B Electro-optical Characteristics (Ta = 25C, VDD = 5V, Clock frequency: 1MHz, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm), Without S/H mode) Item Sensitivity 1 Sensitivity 2 Sensitivity nonuniformity Saturation output voltage Dark voltage average Dark signal nonuniformity Image lag Dynamic range Saturation exposure 5V current consumption Total transfer efficiency Output impedance Offset level Symbol R1 R2 PRNU VSAT VDRK DSNU IL DR SE IVDD TTE ZO VOS Min. 180 -- -- 0.8 -- -- -- -- -- -- 92 -- -- Typ. 240 3500 5.0 1.0 3.0 6.0 1 333 0.004 5.0 98.0 250 2.85 Max. 300 -- 10.0 -- 6.0 12.0 -- -- -- 10 -- -- -- Unit V/(lx * s) V/(lx * s) % V mV mV % -- lx * s mA % V Remarks Note 1 Note 2 Note 3 -- Note 4 Note 4 Note 5 Note 6 Note 7 -- -- -- Note 8 Note) 1. For the sensitivity test light is applied with a uniform intensity of illumination. 2. Light sourse: LED = 660nm 3. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1. PRNU = (VMAX - VMIN)/2 VAVE x 100 [%] The maximum output of all the valid pixels is set to VMAX, the minimum output to VMIN and the average output to VAVE. 4. Integration time is 10ms. 5. Typical value is used for clock pulse and readout pulse. VOUT = 500mV. 6. DR = VSAT VDRK When optical integration time is shorter, the dynamic range sets wider because dark voltage is in proportion to optical integration time. 7. SE = VSAT R1 8. VOS is defined as indicated below. D Vout D D SI VOS GND -3- Clock Timing Diagram (without S/H mode) 5 ROG 0 0 1 2 3 2086 5 CLK 0 D1 D2 D3 D4 D5 D10 D11 D12 D13 D14 D30 D31 D32 S1 S2 S3 S4 S2045 S2046 S2047 S2048 D33 D34 D35 VOUT Optical black (18 pixels) Dummy signal (32 pixels) Effective picture elements signal (2048 pixels) Dummy signal (6 pixels) 1-line output period (2086 pixels) Without S/H mode (Pin 4 VDD) Note) 2088 or more clock pulse are required. D36 D37 D38 1 -4- ILX554B Clock Timing Diagram (with S/H mode) 5 ROG 0 0 1 2 3 2086 5 CLK 0 D0 D1 D2 D3 D4 D5 D10 D11 D12 D13 D14 D30 D31 D32 S1 S2 S3 S4 VOUT Optical black (18 pixels) Dummy signal (33 pixels) Effective picture elements signal (2048 pixels) 1-line output period (2087 pixels) With S/H mode (Pin 4 GND) Note) 2088 or more clock pulse are required. S2045 S2046 S2047 S2048 D33 D34 D35 D36 D37 D38 Dummy signal (6 pixels) 1 -5- ILX554B ILX554B CLK Timing (For all modes) t1 t2 CLK t3 t4 Item CLK pulse rise/fall time CLK pulse duty1 1 100 x Symbol Min. 0 40 Typ. 10 50 Max. 100 60 Unit ns % t1, t2 -- t4 / (t3 + t4) ROG, CLK Timing t6 t8 ROG t7 CLK t5 t9 Item ROG, CLK pulse timing 1 ROG, CLK pulse timing 2 ROG pulse rise/fall time ROG pulse period Symbol Min. 0 1000 0 1000 Typ. 3000 3000 10 5000 Max. -- -- -- -- Unit ns ns ns ns t5 t9 t6, t8 t7 -6- ILX554B CLK, VOUT Timing (Note 1) (Note 3) CLK t10 t11 VOUT VOUT (Note 2) t12 Item CLK-VOUT 1 CLK-VOUT 2 CLK-VOUT (with S/H) 3 Symbol Min. 20 55 20 Typ. 100 210 150 Max. 250 410 250 Unit ns ns ns t10 t11 t12 Note 1) fck = 1MHz, CLK pulse duty = 50%, CLK pulse rise/fall time = 10ns Note 2) Output waveform when internal S/H is in use. Note 3) indicates the correspondence of clock pulse and data period. -7- ILX554B Example of Representative Characteristics Spectral sensitivity (Typ.) (Ta = 25C) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 600 700 Wavelength [nm] 800 900 1000 Dark voltage rate vs. Ambient temperature (Typ.) 10 Dark voltage rate 1 0.1 0 10 20 30 40 50 60 Ta - Ambient temperature [C] -8- ILX554B Output voltage rate vs. Integration time (Typ.) 10 Current consumption rate vs. Clock frequency (Typ.) 2.0 1 Current consumption rate 1 10 Integration time [ms] 100 1.5 Output voltage rate 1.0 0.5 0.1 0 0 0.5 1.0 1.5 2.0 Clock frequency [MHz] Offset level vs. VDD (Typ.) 3.2 3.1 3.0 Offset level [V] 2.9 2.8 2.7 2.6 2.5 2.4 4.50 Offset level [V] 4.75 5.00 VDD [V] 5.25 Offset level vs. Ambient temperature (Typ.) 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 2.4 5.50 0 20 40 60 Ambient temperature [C] -9- ILX554B Application Circuit (Without S/H mode) Note) VDD 0.01 22/10V 22 NC 21 NC 20 VDD 19 GND 18 NC 17 NC 16 NC 15 NC 14 NC 13 NC 12 NC ROG SHSW CLK VOUT NC NC NC NC NC NC 1 2 3 4 100 5 6 7 8 9 10 NC 11 100 3k VOUT CLK ROG Note) This circuit diagram is the case when internal S/H mode is not used. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 10 - ILX554B Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling, be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an eath band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) lonized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates use cartons treated for the prevention of static charges. 2) Notes on handling CCD Cer-DIP package The following points should be observed when handling and installing this package. a) (1) Compressive strength: 39N/surface (Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm Upper ceramic layer 39N 29N 29N 0.9Nm Lower ceramic layer (1) Low-melting glass (2) (3) (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack because the upper and lower ceramic layers are shielded by low-melting glass. (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with a soldering iron. (3) Rapid cooling or heating. (4) Applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes demage to the glass abd other defects. Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount image sensors, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. - 11 - ILX554B 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface blow it off with an air blower. (For dirt stuck through static electricity, ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. 7) Normal output signal is not obtained immediately after device switch on. Use the output signal added 22500 pulses or above to CLK clock pulse. - 12 - Package Outline Unit: mm 22 pin DIP (400mil) 41.6 0.5 12 22 5.0 0.3 1 11 4.0 0.5 0.3 M PACKAGE STRUCTURE PACKAGE MATERIAL Cer-DIP LEAD TREATMENT TIN PLATING LEAD MATERIAL 42 ALLOY PACKAGE MASS 5.20g DRAWING NUMBER LS-A20(E) 4.35 0.5 2.54 0.51 3.65 - 13 - 1. The height from the bottom to the sensor surface is 2.45 0.3mm. 2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5. 0.25 H No.1 Pixel 10.0 0.5 V 0 to 9 6.46 0.5 28.672 (14m X 2048Pixels) ILX554B Sony Corporation |
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